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The imaging for additive metalization uses a permanent dry-film photoresist For additional layers of dielectric, an adhesion promoter is applied to the surface copper Figure 233 outlines the IBSS process 23312 Surface Laminar Circuits SLC technology was the first of the PID microvia, build-up technologies to reach the interconnect market in high volume Development of SLC technology began during the late 1980s at IBM (Yasu, Japan), and the first product was introduced in 19901 The first flip-chip, direct-chip-attach (FC/DCA) product employing SLC technology was shipped from Yasu in 1992, and in 1995 IBM Endicott, New York, shipped its first printed wiring boards that utilized SLC technology2 Used by many original equipment manufacturers (OEMs) in Japan, the SLC process provided the high-density interconnect technology for Sony s first digital Camcorder, the DCR-PC7, seen in Fig 234.

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This eight-layer build-up structure had two SLC layers on each side of a four-layer core The assembly density of this was over 612 pins per sq in due to the wall-to-wall 05 mm pitch chip scale package (CSP) used3 The most suitable photosensitive dielectric was the photo-imageable solder masks, due to their proven compatibility with printed circuit assembly processes, ability to withstand exposure to service environments, and possession of the necessary via-imaging characteristics SLC technology was originally developed and implemented with a liquid PID solder mask applied by curtain coating In 1995, it was also qualified with a dry-film PID with virtually identical electrical properties The dry-film version did not require the extensive surface grinding processes that the liquid PID process required PID technology is based on photoimageable polymeric systems to form blind microvias in dielectric material between layers of circuitry.

The use of PIDs allows all microvias on a panel to be formed simultaneously, with no incremental-per-via cost Its use is particularly advantageous on applications with high densities of vias (eg, more than 50,000 on an 18 in 24 in panel)..

23.3.1.2.1 Liquid Versus Dry PID. A typical flowchart of the PID technology fabrication process, including options for multiple build-up layers and a multilayer core, is shown in Fig. 23.5. At this level in the process, PID technology is the same whether a liquid or dry-film PID is used. Liquid and dry-film PIDs do provide slightly different via wall profiles. The liquid PID has tapered via walls, whereas the dry-film PID has essentially vertical via walls. The tapered via walls provide good plating coverage on the via walls and base.Vertical walls allow for a smaller via top opening, and correspondingly smaller capture land for a given via bottom diameter.4, 5 23.3.1.2.2 Tools. The use of a liquid PID requires two unique pieces of equipment: a coater of some variety, either curtain, slot, roller coater or screen printer (with associated drying ovens), and a leveling tool (surface sander). A leveling tool is required to planarize the surface of the cured liquid PID to accommodate fine-line photolithography on the surface. Liquid PID provides a conformal coating over underlying circuit features, producing nonuniform planarity. The leveling operation also removes a lip of exposed PID that overhangs the via openings in these processes. Many liquid PIDs have a self-leveling characteristic and do not require any other leveling.

FIGURE 23.4 The Sony DCR-PC7 digital camcorder utilized the SLC process for the 2+4+2 build-up structure and 0.5 mm CSPs to achieve over 600 connections (pins) per sq. in.

The use of a dry-film PID requires only one unique piece of equipment: a vacuum laminator Vacuum laminators are common at printed circuit fabrication shops; in addition, the capital to obtain one is significantly less than for a curtain or slot coater The dry-film PID has excellent planarization and does not require a leveling process due to the film s low solvent content, low shrinkage, and vacuum lamination process6, 7 PID technologies were originally conceived as an alternative to multilayer lamination as a way to make multilayer PWBs PID technology builds up each surface signal layer on top of the previous layers in a sequential fashion The base under all of the outer build-up layers is a conventional double-sided or multilayer circuit board containing voltage, ground planes, and even signal layers.