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Mechanically drilled and plated holes are used only in the core layers, to make connections to the backside of the laminate base and accommodate mounting pinned componentsThere is greater wiring density to use plated through holes (PTHs), which extend only through the base printed circuit structure and not through the build-up layers, especially when two or more build-up layers are used Figure 236 provides additional details of the SLC manufacturing process of multilayer printed circuit boards8, 9 23313 DV Mult-PID DV Mult-PID is from NECThis structure uses a PID primarily as an integrated circuit (IC) substrate and for high-density electronic products It is capable of three build-up layers per side Figure 237 shows a typical NEC high-density board The use of a dry-film PID requires only one unique piece of equipment: a vacuum laminator.

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Vacuum laminators are common at printed circuit fabrication shops; in addition, they cost much less than a curtain or slot coaterThe dry-film PID has excellent planarization, does not require a leveling process due to the film s low solvent content, low shrinkage, and vacuum lamination The modified structure of DV Multi-AD uses laminates and RCC for the build-up layers and fully additive electroless plating Figure 238 illustrates this structure and manufacturing process..

Laser Via Technologies(3 5), [3 6], [7 10] Circled processes 3, 4, and 5, as well as squared 3 through 10 in Fig. 23.1, utilize a laser drill via generation technique. This process was first used in the late 1970s to drill small holes in G-10 laminate for buried vias in mainframe computer boards by IBM for its 3081 system and by Burroughs. (Attempts to find pictures of these products proved unfruitful.) The Hewlett

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Packard laser-drilled Finstrate family of boards, first produced in 1983, is shown in 22 Siemens laser-drilled microwiring was produced since 1987 23321 High-Density Interconnect (HDI) The HDI process developed by General Electric and now owned by Lockheed Martin is the one most similar to IC processes This process is what is called a chips first, as the assembly is done before the substrate is completed and the IC bonding is direct to the substrate It does not use flip-chip or wire bonding, but can utilize unmodified chips directly A number of build-up layers and very fine geometry are possible There are obvious advantages in making multichip modules and in using standard chips The materials and bonding technologies have proven to be very reliable and suitable for military applications The disadvantage is the maximum panel that can be sputtered.

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Future use of PVD/CVD metallization may make this process more cost-effective 233211 Structure The circuit structure of HDI consists essentially of common conventional flex circuits or more advanced microvia flex structures These are purchased for this process The polyimide film is usually 25- or 50-micron adhesiveness The laser ablates away the polyimide to produce blind and through vias The through vias are stopped by the aluminum bonding pads of the integrated circuits By doing this, integrated circuits designed for wire bonding can be directly attached Figure 239 shows a typical HDI structure 233212 Manufacturing Process The process starts with a finished single-sided, double-sided, or multilayer polyimide flex circuitAn adhesive is applied to the flex circuitAll the ICs and components are bonded to the polyimide film layer pair flex circuitry and cured.

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Preface CHAPTER 1 A Quick Review of Special Relativity Frame of Reference Clock Synchronization Inertial Frames Galilean Transformations Events The Interval Postulates of Special Relativity Three Basic Physical Implications Light Cones and Spacetime Diagrams Four Vectors Relativistic Mass and Energy Quiz Vectors, One Forms, and the Metric Vectors New Notation Four Vectors The Einstein Summation Convention Tangent Vectors, One Forms, and the Coordinate Basis Coordinate Transformations

The assembly is turned over and a laser drills down through the flex circuitry to make blind and through vias including opening up the bonding pads on the IC chip Gold, under-bump metallurgy, or C4 bumps are not required The panel goes through tungsten sputtering to metalize the vias and seed the top layer Circuit pattern can be applied, plated, and then etched to complete the circuit The process is diagrammed in Fig 231010, 11.

FIGURE 23.9 Structure for the HDI multilayer substrate with lasered blind vias and direct connection to the ICs.

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