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The manufacturing process for each microvia technology begins with a base core, which may be a simple double-sided board carrying power and ground planes or a multilayer board carrying some signal pattern in addition to power and ground planes. The core usually has plated through holes (PTHs). These PTHs become BVHs. Such a core is often called an active core. 22.6.1 Photovia Process Prior to dielectric material coating by any of the methods described previously, the copper surface of the base core must be treated by an adhesion promotion process to ensure good adhesion of dielectric material to the copper surface. Today, very few manufacturers use oxide treatment for this purpose.The most popular adhesion promotion treatment is a special etching process offered by many suppliers of chemicals. This step is common to all microvia processes. Dielectric resin is semicured after coating to eliminate tackiness, and then the hole pattern is exposed by photoexposure processing. The usual photodeveloping process creates microvia holes and the dielectric is fully cured, typically at 160 C for about 1 hour. Then, the panel goes through a permanganate etching process to remove any residual resin at the bottom of the hole and simultaneously create microporous surfaces that act as an anchor and ensure desirable peel strength after copper plating. The level of peel strength is controversial. Minimum peel strength required for chip package substrates is about 600 g/cm2, but motherboard users, particularly cell phone makers, demand a minimum of 1.0 kg/m2 or more in order for cell phone handsets to withstand drop tests. Laser via materials usually yield stronger peel strength because of fillers that can be added to dielectric resin. When etched, these fillers generate a superior microporous surface structure needed for strong peel strength.

After permanganate etching, the panel is catalyzed and metallized in an electroless copper bath and panel-plated galvanically to desired thickness Some photovia process practitioners roughen the resin surface mechanically by brushing or liquid horning prior to catalyzing Then, the conductor pattern is formed by dry-film tenting and etching Some manufacturers prefer to use the pattern-plating method for this purpose Very few microvia board manufacturers use direct metallization methods for metallizing holes prior to galvanic plating Several Japanese manufacturers use electroless copper all the way to the desired thickness in panel plating and use a positive electrodeposited (ED) system to achieve fine lines and very small annular rings One important step in microvia hole board fabrication when resin is the dielectric choice, whether the process is photovia or laser via, is the removal of residual catalysts (normally palladium) entrapped in a microporous surface that can cause migration.

The process used in this step is normally a trade secret Photovia processing is now used primarily to fabricate semiconductor chip package substrates because a large number of holes can be formed in one photoexposure and development step However, as mentioned previously, photovia processing suffers more from material shrinkage than laser via processing after full cure, and hole locations tend to move randomly, which makes subsequent registration for patterning difficult Because of this problem, photovia users limit the size of the panel to be much smaller than the usual panel size prevalent in motherboard fabrication to about 400 mm 400 mm Small hole formation is also difficult with the photovia processAs a result, even makers of package substrates are now resorting more to laser via processes as the laser-drilling speed is being improved Photovia process users engaged in mass production are found only in Japan today.

All photodielectric processes have certain characteristics in general Table 2211 lists the typical processing factors A standard photovia process sequence is described in Fig 2218a..

TABLE 22.11 Four Typical Photodielectrics (Three Epoxy and One Polyimide) and the Processing Parameters for Coating, Exposure, Developing, Desmears, and Metallization Product A Product Material Preclean Apply PID Thickness Drying Exposure Heat bump Development Final cure Roughen Swell Etch Neutralize Metallize: electroless Cu Bake Electroplate L-PID, negative Epoxy Chemical clean Curtain coat 150 400 cps 50 mm 15 h @ 90 C 800 1,200 mJ/cm2 15 h @ 90 C Aqueous proprietary 75 min @ 35 C UV: 1.0 J/cm2 + 60 h @ 145 C 4 h @ 65 C 4 h @ 80 C 6 h @ 50 C 0.3 0.5 mm 20 h @ 90 C Product B L-PID, negative Epoxy Pumice jet Curtain coat 200 600 cps 50 mm 6 h @ 25/40 C 3 h @ 140 C 800 1,600 mJ/cm2 12 h @ 125 C Organic GBL 60 min @30 C 60 h @ 150 C Product C L-PID, negative Polyimide Br. oxide Extrusion coat 12,000 25,000 cps 37 mm 5 h @ 25 C 15 h @ 125 C 2,000 3,000 mJ/cm2 N.R. Organic proprietary 150 min @ 30 C 120 h @ 175 C Product D DF-PID, negative Epoxy Chemical clean Vac, Iam. 60 s @ 65 C 63 mm N/A 700 1,200 mJ/cm2 20 h @ 85 C Aqueous proprietary 60 min @ 35 C UV: 2 J/cm2 + 60h @ 150 C 5 h @ 60 C 10 h @ 75 C 3 h @ 25 C 0.4 mm 15 h @ 90 C